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bn:03133754n
Noun Named Entity
Categories: MIPS microprocessors, Superscalar microprocessors, MIPS implementations
EN
R10000  Architecture with Non-sequential Dynamic Execution Scheduling  R12000  R12000A  R14000
EN
The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture developed by MIPS Technologies, Inc. Wikipedia
Definitions
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Sources
EN
The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture developed by MIPS Technologies, Inc. Wikipedia
MIPS microprocessor Wikidata
IS A
central processing unit
DEVELOPER
MIPS Technologies
INSTRUCTION SET
MIPS architecture
MANUFACTURER
NEC
Toshiba
Wikipedia
EN
R10000
Wikidata
EN
R10000
Wikipedia Redirections
EN
Architecture with Non-sequential Dynamic Execution Scheduling, R12000, R12000A, R14000, R14000A, R16000, R16000A, R18000

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